Download Analog Integrated Circuit Design Automation: Placement, by Ricardo Martins, Nuno Lourenço, Nuno Horta PDF

By Ricardo Martins, Nuno Lourenço, Nuno Horta

This publication introduces readers to numerous instruments for analog structure layout automation. After discussing the situation and routing challenge in digital layout automation (EDA), the authors evaluate a number of automated structure new release instruments, in addition to the newest advances in analog layout-aware circuit sizing. The dialogue contains diverse equipment for computerized placement (a template-based Placer and an optimization-based Placer), a fully-automatic Router and an empirical-based Parasitic Extractor. The ideas and algorithms of all of the modules are completely defined, allowing readers to breed the methodologies, increase the standard in their designs, or use them as start line for a brand new software. the entire equipment defined are utilized to functional examples for a 130nm layout technique, in addition to placement and routing benchmark sets.

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Extra info for Analog Integrated Circuit Design Automation: Placement, Routing and Parasitic Extraction Techniques

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Aided Des. Integr. Circuits Syst.  Syrzycki, A tool for automated analog CMOS layout module generation and placement. IEEE Can. Conf. Elect. Comput. Eng. 1, 416–421 (2002) 9.  Smith, Introduction to Evolutionary Computing (Springer, Berlin, 2003) 10.  Shahookar, Macro-cell and module placement by genetic adaptive search with bitmap-represented chromosome. Integr.  12(1), 49–77 (1991) 11.  Vornberger, Hybrid genetic algorithms for constrained placement problems. IEEE Trans. Evol. Comput. 1(4), 266–277 (1997) 12.

The solution space is greatly reduced as only feasible regions (admissible placements) of the solution space are explored. However, depending on the topological representation used, the optimal solution can be left out of the search space. Furthermore, since the optimization kernel only changes the relative positioning, symmetry-feasible conditions by means of structure scan or post-­processing in order to penalize, avoid or fix the symmetries violated each time the typically SA-based kernel perturbs the structure must be derived for each representation.

In these automatic approaches only results for single-net problem solving are presented, which focus on the WT generation, and the applicability to obtain design rulecorrect routings for the set of conflicting nets of real analog IC design cases remains to be proved [65–71]. In the traditional automatic approaches for design rule-correct layouts [4, 7, 8, 51, 52, 62–64, 78], besides the traditional deterministic and error-prone implementations, the exact location of the single-port terminals may be either defined in the generation/import of the modules, selected manually or by pin assignment problem solving, which lead to higher setup times and/or sub-optimal solutions.

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