By Himanshu Bhatnagar
Advanced ASIC Chip Synthesis: utilizing Synopsys® DesignCompiler® and PrimeTime® describes the complicated recommendations and methods used for ASIC chip synthesis, formal verification and static timing research, utilizing the Synopsys suite of instruments. furthermore, the whole ASIC layout movement technique distinctive for VDSM (Very-Deep-Sub-Micron) applied sciences is roofed intimately.
The emphasis of this publication is on real-time program of Synopsys instruments used to strive against numerous difficulties visible at VDSM geometries. Readers may be uncovered to an efficient layout method for dealing with advanced, sub-micron ASIC designs. value is put on HDL coding kinds, synthesis and optimization, dynamic simulation, formal verification, DFT experiment insertion, hyperlinks to format, and static timing research. At each one step, difficulties on the topic of every one section of the layout move are pointed out, with suggestions and work-arounds defined intimately. furthermore, the most important matters on the topic of structure, together with clock tree synthesis and back-end integration (links to structure) also are mentioned at size. in addition, the e-book comprises in-depth discussions at the fundamentals of Synopsys know-how libraries and HDL coding types, distinct in the direction of optimum synthesis options.
Advanced ASIC Chip Synthesis: utilizing Synopsys® DesignCompiler® and PrimeTime® is meant for an individual who's interested by the ASIC layout method, ranging from RTL synthesis to ultimate tape-out. aim audiences for this booklet are training ASIC layout engineers and graduate scholars project complex classes in ASIC chip layout and DFT strategies.
From the Foreword:
`This booklet, written via Himanshu Bhatnagar, presents a accomplished evaluate of the ASIC layout circulate detailed for VDSM applied sciences utilizing the Synopsis suite of instruments. It emphasizes the sensible matters confronted through the semiconductor layout engineer when it comes to synthesis and the mixing of front-end and back-end instruments. conventional layout methodologies are challenged and distinctive strategies are provided to aid outline the following iteration of ASIC layout flows. the writer offers a number of sensible examples derived from real-world events that may turn out important to training ASIC layout engineers in addition to to scholars of complicated VLSI classes in ASIC design'.
Dr Dwight W. Decker, Chairman and CEO, Conexant platforms, Inc., (Formerly, Rockwell Semiconductor Systems), Newport seashore, CA, USA.
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Extra resources for Advanced ASIC Chip Synthesis: Using Synopsys® Design Compiler™ and PrimeTime®
Let's assume that the design has been floorplanned. Also, the clock tree has been inserted in the design by the layout tool. The clock tree insertion modifies the existing structure of the design. In other words, the netlist in the layout tool is different from the original netlist present in DC. This is because of the fact that the design present in the layout tool contains the clock tree, whereas the original design in DC does not contain this information. Therefore, the clock tree information should somehow be transferred to the design residing in DC or PT.
Spf # for clocks etc. 2 Post-Layout Optimization The post-layout optimization or PLO may be performed on the design to improve or fix the timing requirements. DC provides several methods of fixing timing violations, through the in-place optimization (or IPO) feature. As before, DC also makes use of the physical placement information to perform location based optimization (LBO). In this example, we will use the cell resizing and buffer insertion feature of the IPO to fix the hold-time violations.
Let us presume that the design has been fully routed with minimal congestion and area . The finished layout surface must then be extracted to get the actual parasitic capacitances and interconnect RC delays. Depending upon the 36 Chapter 2 layout tool and the type of extraction, the extracted values are generally written out in the SDF format for the interconnect RC delays, while the parasitic information is generated as a string of set joad commands for each net in the design. In addition, if a hierarchical place and route has been performed, the physical placement location of cells in the PDEF format should also be generated.