By Himanshu Bhatnagar
Advanced ASIC Chip Synthesis: utilizing Synopsys® Design Compiler® actual Compiler® and PrimeTime®, Second Edition describes the complicated thoughts and methods used in the direction of ASIC chip synthesis, actual synthesis, formal verification and static timing research, utilizing the Synopsys suite of instruments. moreover, the whole ASIC layout movement technique certain for VDSM (Very-Deep-Sub-Micron) applied sciences is roofed intimately.
The emphasis of this publication is on real-time software of Synopsys instruments, used to wrestle numerous difficulties visible at VDSM geometries. Readers should be uncovered to an efficient layout method for dealing with complicated, sub-micron ASIC designs. value is put on HDL coding types, synthesis and optimization, dynamic simulation, formal verification, DFT experiment insertion, hyperlinks to structure, actual synthesis, and static timing research. At each one step, difficulties similar to every part of the layout circulate are pointed out, with options and work-around defined intimately. furthermore, an important concerns similar to structure, including clock tree synthesis and back-end integration (links to structure) also are mentioned at size. in addition, the publication includes in-depth discussions at the foundation of Synopsys expertise libraries and HDL coding kinds, precise in the direction of optimum synthesis resolution.
objective audiences for this publication are training ASIC layout engineers and masters point scholars project complex VLSI classes on ASIC chip layout and DFT recommendations.
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